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"Mostly missless memory in the Mill CPU: Avoiding the pain of cache misses in a statically-scheduled architecture" -Ivan Godard, Out-of-the-Box ComputingUploaded 24-10-13Colloquium on Computer Systems Seminar Series (EE380) presents the current research in design, implementation, analysis, and use of computer systems. Topics range from integrated circuits to operating systems and programming languages. It is free and open to the public, with new lectures each week.Learn more: http://bit.ly/WinYX50:00 Introduction1:02 The Mill Architecture3:37 Wide issue5:02 Exposed pipeline9:16 The memory hierarchy11:10 The load problem12:08 Every CPU's goal - hide load latency13:20 Hardware approach - dynamic scheduling22:18 Several different load problems...24:36 Mill "deferred loads"28:56 Deferred loads vs. alternatives32:57 Reordering constraints34:50 So eliminate aliasing35:53 Alias immunity37:09 Loads across control flow38:14 Pickup loads39:41 Compiler strategy41:32 The trade-off42:22 Implementation - the retire station43:33 Implementation - stream monitoring46:06 Retire station allocation48:00 The fine print #150:33 The fine print #251:29 When stores miss...52:45 Valid bits58:50 Hierarchy from 40,000 ft. Learn more about your ad choices. Visit megaphone.fm/adchoices
